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| 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 TMP88CP77/S77/U77 2.6.2 Control The timer / counter 1 is controlled by a timer / counter 1 control register (TC1CR) and two 16-bit timer registers (TREG1A and TREG1B). Reset does not affect TREG1A and TREG1B. Timer Register 1 TREG1A (00016, 00017H) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TREG1AH (00017H) TREG1AL (00016H) Write only TREG1B (00012, 00013H) TREG1BH (00013H) TREG1BL (00012H) Read only Timer Counter 1 Control Register 7 6 SCAP1 MCAP1 METT1 5 4 3 2 1 0 TC1CR (00014H) "1" TC1S TC1CK TC1M (Initial value: *000 0000 ) 00: Timer / external trigger timer / event counter mode TC1M TC1 operating mode select 01: Window mode 10: Pulse width measurement mode 11: reserved NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV1CK = 0 TC1CK TC1 source clock select [Hz] 00 01 10 11 00: Stop & counter clear TC1S TC1 start control 01: Command start 10: Reserved 11: External trigger start SCAP1 MCAP1 METT1 Software capture control Pulse width measurement mode control External trigger timer mode control 0: 0: Double edge capture 0: Trigger start 1: Software capture trigger 1: Single edge capture 1: Trigger start & stop fc/211 fc/2 7 DV7CK = 1 DV1CK = 0 fs/23 fc/2 7 DV1CK = 1 fc/212 fc/2 8 DV1CK = 1 fs/23 fc/2 8 SLOW, SLEEP mode fs/23 fc/23 fc/24 fc/23 fc/24 Write only External clock (TC1 pin input) Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz] Note 2: Writing to the lower byte of the timer registers (TREG1AL, TREG1BL), the comparison is inhibited until the upper byte(TREG1AH, TREG1BH) is written. Only the lower byte of the timer registers can not be changed. After writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored. Note 3: Set the mode, source clock, edge (including INT2ES) when TC1 stops (TC1S=00). Note 4: Software capture can be used in only timer and event counter modes. SCAP1 is automatically cleared to "0" after capturing. Note 5: Values to be loaded to timer registers must satisfy the following condition. TREG1A>0 Note 6: TC1CR and TREG1A are write-only registers and must not be used with any of the read-modify-write instructions such as SET, CLR, etc. Note 7: Please use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Please read the capture value in a capture enabled condition. Note 8: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Figure 2-19. Timer Registers and TC1 Control Register 3-77-62 2007-10-23 2007-10-23 2007-10-23 2007-10-23 TMP88CP77/S77/U77 (4) Window mode Counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC1 pin input (window pulse) and an internal clock. The contents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Positive or negative logic for the TC1 pin input can be selected. Edge selection is the same as for INT2 pin. Setting SCAP1 to "1" transfers the current contents of up-counter to TREG1B. It is necessary that the maximum applied frequency be such that the counter value can be analyzed by the program. That is; the frequency must be considerably slower than the selected internal clock. Command start TC1 pin input Internal clock Up-counter TREG1A INTTC1 interrupt (a) Positive logic (at INT2ES=0) Command start 0 ? 7 1 2 3 4 5 6 7 0 1 2 3 Match detect Counter clear TC1 pin input Internal clock Up-counter TREG1A INTTC1 interrupt (b) Negative logic (at INT2ES=1) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 90 1 Figure 2-23. Window Mode Timing Chart (5) Pulse width measurement mode Counting is started by the external trigger (set to external trigger start by TC1S). The trigger can be selected either the rising or falling edge of the TC1 pin input. The source clock is used an internal clock. On the next falling (rising) edge, the counter contents are transferred to TREG1B and an INTTC1 interrupt is generated. The counter is cleared when the single edge capture mode is set. When double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred to TREG1B. If a falling (rising) edge capture value is required, it is necessary to read out TREG1B contents until a rising (falling) edge is detected. Falling or rising edge is selected with INT2ES, and single edge or double edge is selected with MCAP1 (bit 6 in TC1CR). Note: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value. 3-77-66 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 TMP88CP77/S77/U77 I2C bus mode control The following registers are used to control the serial bus interface (SBI-ver.C) and monitor the operation status in the I2C bus mode. Serial Bus Interface Control Register 1 SBICR1 (00020H) 7 6 BC 5 4 ACK 3 SWRST 2 1 SCK ACK = 0 BC Number of Clock 8 1 2 3 4 5 6 7 Bits 8 1 2 3 4 5 6 7 0 (Initial value: 0000 0000) ACK = 1 Number of Clock 9 2 3 4 5 6 7 8 Bits 8 1 2 3 4 5 6 7 Read/ Write Read/ Write Write only 2.10.4 000 001 BC Number of transferred bits 010 011 100 101 110 111 ACK SWRST Acknowledge mode specification Initiate a internal of SBI 0: Acknowledge not returned to transmitter. 1: Acknowledge returned to transmitter. 0: 1: Initialized (Clearing "0" after initialized) 000:Reserved (Note4) 001:Reserved (Note4) 010: 58.8 kHz 011: 30.3 kHz 100: 15.4 kHz 101: 7.75 kHz 110: 3.89 kHz 111:Reserved SCK Serial clock selection at fc = 8 MHz (Output on SCL pin) Write only Note 1: fc ; High-frequency clock [Hz] Note 2: Set the BC to "000" before switching to 8-bit SIO bus mode. Note 3: SBICR1 is write-only registers, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. Note 4: This I2C bus circuit does not support the Fast mode. It supports the Standard mode only. Although the I2C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C specification is not guaranteed in that case. Serial Bus Interface Data Buffer Register SBIDBR (00021H) 7 6 5 4 3 2 1 0 Read / Write Note 1: For writing transmitted data, start from the MSB (bit 7). Note 2: Cannot read the data which was written into SBIDBR, since a write data buffer and a read data buffer are independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc. Note 3: The data which was written into SBIDBR is cleared to "0" when INTSBI is generated. I2C bus Address Register I2CAR (00022H) 7 SA6 SA ALS 6 SA5 5 SA4 4 Slave address SA3 SA2 SA1 SA0 3 2 1 0 ALS (Initial value: 0000 0000) Write only 88CP77/S77/U77 slave address selection Address recognition mode specification 0: Slave address recognition 1: Non slave address recognition Note: I2CAR is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. Figure 2-41.Serial Bus Interface Control Register 1, Serial Bus Interface Data Buffer Register and I2C Bus Address Register In The I2C Bus Mode 3-77-93 2007-10-23 2007-10-23 TMP88CP77/S77/U77 (1) Acknowledge mode specification Set the ACK (bit 4 in SBICR1) to "1" for operation in the acknowledge mode. The 88CP77/S77/U77 generates an additional clock pulse for an acknowledge signal when operating in the master mode. In the transmitter mode during the clock pulse cycle, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low level in order to generate the acknowledge signal. Reset the ACK for operation in the non-acknowledge mode. The 88CP77/S77/U77 do not generate a clock pulse for the acknowledge signal when operating in the master mode. In the acknowledge mode, the 88CP77/S77/U77 counts a clock pulse for the acknowledge signal when operating in the slave mode. During the clock pulse, when the received slave address is the same as the value set at the I2CAR or when a GENERAL CALL is received, the SDA pin is set to the low level in order to generate the acknowledge signal. In the transmitter mode during the clock pulse cycle after matching the slave addresses or receiving a GENERAL CALL, the SDA pin is released in order to receive the acknowledge signal from the receiver. In the receiver mode during the clock pulse cycle, the SDA pin is set to the low level in order to generate the acknowledge signal. In non-acknowledge mode, the 88CP77/S77/U77 does not count a clock pulse for the acknowledge signal when operating in the slave mode. (2) Number of transfer bits The BC (bits 7 to 5 in SBICR1) is used to select a number of bits for transmitting and receiving data. Since the BC is cleared to "000" as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. Other than these, the BC retains a specified value. (3) Serial clock a. Clock source The SCK (bits 2 to 0 in SBICR1) is used to select a maximum transfer frequency output from the SCL pin in the master mode. Set a communication baud rate that meets the I2C bus specification, such as the shortest pulse width of tLOW, based on the equations shown below.In both master mode and slave mode, a pulse width of at least 4 machine cycles is required for both high and low levels. tHIGH tLOW 1/fscl tLOW = 2 n /fc tHIGH = 2n /fc + 8/fc fscl = 1/(tLOW + tHIGH) Note: fc ; High-frequency clock SCK (bits 2 to 0 in the SBICR1) 000 001 010 011 100 101 110 n 4 5 6 7 8 9 10 Figure 2-43. Clock Source 3-77-95 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 |
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